1. Field of the Invention
The invention in general relates to the structure and fabrication of integrated circuits and more particularly to a structure and fabrication process for a circuit in which a channel of a transistor is located on the sidewall of its gate.
2. Statement of the Problem
As is well-known, integrated circuits, sometimes called semiconductor devices, are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer, which wafer is subsequently sawed into hundreds of identical dies or chips. The advantages of building integrated circuits with smaller individual circuit elements so that more and more circuitry may be packed on a single chip are well-known: electronic equipment becomes less bulky, reliability is improved by reducing the number of solder or plug connections, assembly and packaging costs are minimized, and improved circuit performance, in particular higher clock speeds. However, smaller size can also lead to problems, such as greater chances of current leakage across boundaries where current in not supposed to flow. Thus circuit structures and fabrication processes that reduce the physical space occupied by a circuit and at the same time do not increase or even reduce such current leakage problems are extremely useful in integrated circuit technology.
While integrated circuits are commonly referred to as "semiconductor devices" they are in fact fabricated from various materials which are either electrically conductive, electrically non-conductive, or electrically semiconductive. Silicon, the most commonly used semiconductor material, can be used in either the single crystal or polycrystalline form. In the integrated circuit fabrication art, polycrystalline silicon is usually called "polysilicon" or simply "poly", and shall be referred to as such herein. Both forms of silicon may be made conductive by adding impurities to it, which is commonly referred to as "doping". If the doping is with an element such as boron which has one less valence electron than silicon, electron "holes" become the dominant charge carrier and the doped silicon is referred to as P-type silicon. If the doping is with an element such as phosphorus which has one more valence electron than silicon, additional electrons become the dominant as N-type silicon.
CMOS (Complimentary Metal Oxide Semiconductor) technology is currently the most commonly used integrated circuit technology, and thus the present invention will be described in terms of silicon-based CMOS technology, although it is evident that it may find uses in other integrated circuit technologies. The term CMOS is now-.loosely applied to mean any integrated circuit in which both N-channel and P-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) are used in a complimentary fashion. It should be noted here that because the dominant carrier in a MOSFET occurs in an inversion layer, the channel of an N-channel MOSFET is actually doped P-type and the channel of a P-channel MOSFET is actually doped N-type. CMOS integrated circuit fabrication may begin with a lightly-doped P-type silicon substrate, a lightly-doped N-type silicon substrate, or lightly-doped epitaxial silicon (deposited crystalline silicon) on a heavily doped substrate. For the sake of simplicity, the invention will be described using lightly-doped P-type silicon as the starting material, although it may be implemented with other materials as the starting point. If other materials are used as the starting point, there may be differences in materials and structure as is well-known in the art, e.g. with N-type silicon as the starting point dopant types may be reversed, or P-type wells may be introduced.
SRAM (Static Random Access Memory) are one of the most densely-packed integrated circuits commonly manufactured today. Thus a structure and process that permits smaller physical circuit structures without increasing leakage problems, or even diminishing leakage problems, and which is applicable to SRAM would be particularly valuable.
The business of fabricating CMOS semiconductor devices is a very competitive, high-volume business. Thus manufacturing efficiency is highly important. Product quality and reliability are also highly important. It is well-known in the art that reducing the number of mask steps in the integrated manufacturing process not only reduces manufacturing costs and time but also generally increases the quality and reliability of the end product, since the opportunities for disabling defects to occur are reduced. This in turn feeds back into further reduced manufacturing costs since scrapped product is reduced. Thus, a circuit structure and process that not only permits more compact devices but also reduces the number of mask steps would therefore be highly desirable.
A typical state-of-the-art SRAM and its fabrication process are described in "A 0.1 .mu.A Standby Current, Bouncing-Noise-immune 1 Mb SRAM" by Manabu Ando et al. in the IEEE Journal of Solid State Circuits, V. 24, No. 6, December, 1989, pp. 1708-1713. As can be seen in FIG. 9, the PMOS load transistor (indicated by the P+ doping) is not self-aligned and thus requires significant masking and space. This reference also discloses that providing a gate/drain or channel/drain offset reduces off current, I(off), in PMOS thin-film transistors (TFT's). However, the offset discloses compounds the alignment problem and adds additional physical size to the PMOS load transistor. The above reference pertains to 1 Mb SRAM. However users of SRAM are now demanding 4 Mb and 16 Mb SRAM. Thus a need exists for an integrated circuit which is more compact and still has performance equal to or better than the prior art SRAM.
3. Solution to the Problem
The present invention provides for using the sidewall of a gate layer to gate a channel of a transistor; in the preferred embodiment, the sidewall of one transistor, previously formed in the fabrication process, as the gate of a second transistor.
The invention also provides for novel self-aligning of transistor parts; in particular the invention provides a novel transistor structure that provides for a self-aligned PMOS load transistor in an SRAM circuit.
In providing the above structure and process, the invention provides an integrated circuit that is more compact than prior art integrated circuits.
The invention further provides an integrated circuit structure and process that requires fewer mask steps; in particular it provides a structure and process that does not require a mask for the SRAM PMOS load transistor channel definition.
The invention in addition provides a gate/drain offset that takes up little additional physical space.
The present invention is particularly applicable to SRAM in that in one embodiment it applies to circuits in which gates of two or more transistors are shorted together, which is a common SRAM circuit design. Once its use in SRAM is understood, however, it is evident that it can be applied in other circuits also.